EC8392 DIGITAL Electronics (DE)
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4. Quine McCluskey method of minimization** UNIT-2 1. Magnitude comparator 2. Prob to implement on gate
4. State minimization
5. Design of synchronous sequential circuit UNIT-4
1. Asynchronous circuit related problem** 2. Cycle and races Don't share as screenshot --Stuff Sector
**Very important questions are bolded and may be asked based on this topic
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*These questions are expected for the exams This may or may not be asked for exams All the best.... from admin Santhosh
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Number Systems – Decimal, Binary, Octal, Hexadecimal, 1‘s and 2‘s complements, Codes – Binary, BCD, Excess 3, Gray, Alphanumeric codes, Boolean theorems, Logic gates, Universal gates, Sum of products and product of sums, Minterms and Maxterms, Karnaugh map Minimization and Quine-McCluskey method of minimization.
UNIT II COMBINATIONAL CIRCUIT DESIGN
Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look ahead Adder,
BCD Adder, Multiplexer, Demultiplexer, Magnitude Comparator, Decoder, Encoder, Priority Encoder.
UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS
Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables, Triggering of FF, Analysis and
design of clocked sequential circuits – Design – Moore/Mealy models, state minimization, state assignment, circuit implementation – Design of Counters- Ripple Counters, Ring Counters, Shift registers, Universal Shift Register.
UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS
Stable and Unstable states, output specifications, cycles and races, state reduction, race free assignments, Hazards, Essential Hazards, Pulse mode sequential circuits, Design of Hazard free circuits.
UNIT V MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS
Basic memory structure – ROM -PROM – EPROM – EEPROM –EAPROM, RAM – Static and dynamic RAM – Programmable Logic Devices – Programmable Logic Array (PLA) – Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA) – Implementation of combinational logic circuits using PLA, PAL.Digital integrated circuits: Logic levels, propagation delay, power dissipation, fan-out and fan-in, noise
margin, logic families and their characteristics-RTL, TTL, ECL, CMOS
UNIT I DIGITAL FUNDAMENTALS
Number Systems – Decimal, Binary, Octal, Hexadecimal, 1‘s and 2‘s complements, Codes – Binary, BCD, Excess 3, Gray, Alphanumeric codes, Boolean theorems, Logic gates, Universal gates, Sum of products and product of sums, Minterms and Maxterms, Karnaugh map Minimization and Quine-McCluskey method of minimization.
UNIT II COMBINATIONAL CIRCUIT DESIGN
Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look ahead Adder,
BCD Adder, Multiplexer, Demultiplexer, Magnitude Comparator, Decoder, Encoder, Priority Encoder.
UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS
Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables, Triggering of FF, Analysis and
design of clocked sequential circuits – Design – Moore/Mealy models, state minimization, state assignment, circuit implementation – Design of Counters- Ripple Counters, Ring Counters, Shift registers, Universal Shift Register.
UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS
Stable and Unstable states, output specifications, cycles and races, state reduction, race free assignments, Hazards, Essential Hazards, Pulse mode sequential circuits, Design of Hazard free circuits.
UNIT V MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS
Basic memory structure – ROM -PROM – EPROM – EEPROM –EAPROM, RAM – Static and dynamic RAM – Programmable Logic Devices – Programmable Logic Array (PLA) – Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA) – Implementation of combinational logic circuits using PLA, PAL.Digital integrated circuits: Logic levels, propagation delay, power dissipation, fan-out and fan-in, noise
margin, logic families and their characteristics-RTL, TTL, ECL, CMOS